The present invention relates in general to semiconductor devices and, more particularly, to integrated circuits that are formed with a semiconductor die and inductors housed in the same semiconductor package.
Electronic system manufacturers continue to demand integrated circuits with increased levels of functionality and a physically smaller size. The demand is particularly evident with portable wireless communications devices, whose size typically is limited by hundreds of discrete passive components that have not yet been successfully integrated due to their operation at frequencies of 2.5 gigahertz or more. High frequency inductors have proven to be particularly difficult to integrate on a semiconductor die because of the performance degradation resulting from the parasitic substrate capacitance and eddy currents.
One previous approach to integrating inductors has been to form planar spiral inductors and their associated circuitry on the same semiconductor die. However, the quality factor of the planar spiral inductors is low due in part to the parasitic substrate capacitance and eddy currents mentioned above. In addition, the additional processing steps and large die area occupied by the planar inductors has a high cost that has made this approach uneconomical in many applications.
Another approach has been to house a discrete chip inductor and a semiconductor die into the same integrated circuit package. The chip inductors have a high quality factor but the component placement and solder reflow processing step needed to mount the inductor also result in a high overall fabrication cost. Moreover, existing discrete chip inductors have a large physical size that increases the profile of the packaged integrated circuit and precludes their use in many applications.
Hence, there is a need for an integrated circuit and method-of integrating inductors that combines a low fabrication cost, small physical size and high performance.